The present invention relates to a photomask for the transfer of features onto a substrate with use of an exposure unit, a semiconductor device manufacturing system having the photomask, and a semiconductor device manufacturing method using the photomask. Particularly, the present invention is concerned with a photomask having a main feature and sub-features formed in proximity to the main feature.
With advance of the semiconductor device manufacturing technique and by the lithography process, circuit patterns formed on a substrate are becoming more and more fine in size. In the lithography process, using an exposure unit, light emitted from a light source is radiated to a photomask formed with features (hereinafter referred to also as “main feature” or “designed feature”) to be transferred (resolved) onto a wafer, whereby features corresponding to a circuit is transferred onto the substrate (wafer).
For forming a finer circuit pattern it is necessary to transfer features with a high resolution having a sufficient depth of focus (DOF). However, light obtained by passage through a main feature arranged isolatedly cannot afford a sufficient depth of focus due to the wavelength thereof being finite. In this connection there is known a method using a photomask having not only a main feature but also sub-features as sub-resolution assist features (SRAF) arranged near the main feature to improve resolution.
For example, in the specification of U.S. Pat. No. 5,821,014 (Patent Literature 1), the specification of U.S. Pat. No. 5,447,810 (Patent Literature 2) and the specification of U.S. Pat. No. 5,242,770 (Patent Literature 3) it is disclosed that sub-features are arranged at positions apart from the sides of an isolated feature so as to approach the optical profile of massed features.
Attention is now being paid to SoC (System on a Chip) with both logic circuit and memory module formed on the same chip. In the layout of SoC there are included many random patterns. If the aforesaid layout rule of sub-features is applied to such a layout, there can occur a case where a sub-feature overlaps the main feature or sub-feature overlap each other. As a countermeasure to such a conflicted case of sub-features, in the specification of U.S. Pat. No. 6,703,167 (Patent Literature 4) and the specification of U.S. Pat. No. 6,413,683 (Patent Literature 5) there is disclosed a method wherein priorities are given to sub-features, and deformation and/or deletion of sub-features are performed in accordance with the order of priority. Particularly, it is disclosed therein that the transfer of a sub-feature not to be resolved onto a wafer, (intended extra image of SRAF), is prevented by deleting a perpendicularly intersecting portion of sub-features.
[Patent Literature 1]
Specification of U.S. Pat. No. 5,821,014
[Patent Literature 2]
Specification of U.S. Pat. No. 5,447,810
[Patent Literature 3]
Specification of U.S. Pat. No. 5,242,770
[Patent Literature 4]
Specification of U.S. Pat. No. 6,703,167
[Patent Literature 5]
Specification of U.S. Pat. No. 6,413,683